By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit Design comprises the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. each one half discusses a selected to-date subject on new and worthy layout principles within the region of analog circuit layout. every one half is gifted by means of six specialists in that box and state-of-the-art details is shared and overviewed. This ebook is quantity 17 during this profitable sequence of Analog Circuit Design.
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Additional info for Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management
2. Synchronous digital signals that become so fast that analog properties start to become relevant: An example of such signals can be found in the digital loop filter in the PCI-Express example further on in this paper. These are blocks that may still use the standard digital CMOS libraries, but speed or timing constraints have become so critical that a classical digital flow would not be able to achieve timing closure anymore due to the margins that need to be taken in this process at different levels.
A random received eye is computed for different configurations of transmission channels and interference to assure a target bit error rate lower than 1e-12. The best partition between the analog block and DFE follows. Verification of system performances, including both equalization and clock recovery, leads to the second step, consisting in VHDL modeling and simulation of the whole system. VHDL modeling allows using event-based VHDL simulators, minimizing CPU time. Finally, mixed signal simulation allows verification of the analog performances of the designed circuit, including parasitic effects.
Unfortunately, since each portion of the detector must operate at a high clock frequency (often in the GHz range), power consumption can be an issue for retimed data(t) data(t) DQ clk(t) DQ Reg e(t) data(t) clk(t) DQ clk(t) DQ Latch Fig. 4 A bang-bang phase detector e(t) Mixed-Signal Implementation Strategies for High Performance Clock data(t) Delay Delay 51 Delay data(t) D E D E D E BB PD BB PD BB PD clk(t) e(t) e(t) clk(t) Fig. 5 A multi-level bang-bang phase detector this structure. Also, in cases where the jitter on the input data is small, nonlinear behavior may again result in a poorly defined jitter transfer function.
Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management by Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier