By Naveed A. Sherwani
Algorithms for VLSI actual layout Automation, moment Edition is a middle reference textual content for graduate scholars and CAD pros. in line with the very winning First version, it presents a accomplished therapy of the foundations and algorithms of VLSI actual layout, offering the innovations and algorithms in an intuitive demeanour. every one bankruptcy includes 3-4 algorithms which are mentioned intimately. extra algorithms are provided in a a bit of shorter structure. References to complicated algorithms are offered on the finish of every bankruptcy.
Algorithms for VLSI actual layout Automation covers all points of actual layout. In 1992, whilst the 1st variation was once released, the most important on hand microprocessor had a million transistors and used to be fabricated utilizing 3 steel layers. Now we approach with six steel layers, fabricating 15 million transistors on a chip. Designs are relocating to the 500-700 MHz frequency objective. those lovely advancements have considerably altered the VLSI box: over-the-cell routing and early floorplanning have come to occupy a important position within the actual layout circulate.
This moment variation introduces a realistic photo to the reader, exposing the troubles dealing with the VLSI undefined, whereas protecting the theoretical style of the 1st variation. New fabric has been extra to all chapters, new sections were extra to such a lot chapters, and some chapters were thoroughly rewritten. The textual fabric is supplemented and clarified via many useful figures.
Audience: a useful reference for pros in structure, layout automation and actual layout.
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Extra resources for Algorithms for VLSI Physical Design Automation
Geometric information is extracted to compute Resistance and Capacitance. This allows to accurately calculate the timing of each component including interconnect. This process is called Per/ormance Verification. The extracted information is also used to check the reliability aspects of the layout. This process is called Reliability Verification and it ensures that layout will not fail due to electro-migration, self-heat and other effects [Bak90J. Physical design, like VLSI design, is iterative in nature and many steps such as global routing and channel routing are repeated several times to obtain a better layout.
5: Full-custom structure. between Ml and M2 is smaller than the size of the via between higher layers. Typically, metal widths and via sizes are larger for higher layers. The figure also shows that some routing has been completed on top of the blocks. The routing area needed between the blocks is becoming smaller and smaller as more routing layers are used. This is due to the fact that more routing is done on top of the transistors in the additional metal layers. If all the routing can be done on top of the transistors, the total chip area is determined by the area of the transistors.
Extracted description is compared with circuit description to verify its correctness. This process is called Layout Versus Schematics (LVS) verification. Geometric information is extracted to compute Resistance and Capacitance. This allows to accurately calculate the timing of each component including interconnect. This process is called Per/ormance Verification. The extracted information is also used to check the reliability aspects of the layout. This process is called Reliability Verification and it ensures that layout will not fail due to electro-migration, self-heat and other effects [Bak90J.
Algorithms for VLSI Physical Design Automation by Naveed A. Sherwani